Research Notes

All 8 names are different layers of the same AI infrastructure capital expenditure wave, specifically the optical interconnect supercycle. Three themes unified them: 1. AI OPTICAL INTERCONNECT SUPERCYCLE: Hyperscalers scaling GPU clusters to 100,000+ cards cannot use copper at 800G/1.6T speeds — they are mandating optical transceivers inside the data center. This is creating explosive demand across the entire optical supply chain simultaneously: InP substrate materials (AXTI), InP laser sources (SIVEF), transceiver manufacturers (AAOI), signal processing DSPs inside transceivers (MXL), and burn-in test for photonics chips (AEHR). 2. INDIUM PHOSPHIDE (InP) AS CRITICAL MATERIAL: InP is the irreplaceable substrate for high-speed optical devices. AXTI (+600% YTD) and SIVEF (+172% in a month) are the upstream InP supply chain. AXTI makes InP wafers, SIVEF makes InP laser arrays. Both hit record backlogs/partnerships driven by AI optical demand. 3. ADVANCED PACKAGING NEXT GENERATION: LPKFF (+300% YTD) is a German company with near-monopoly on LIDE glass substrate drilling — the technology that will replace organic substrates in chip packaging around 2027-2029. PENG (+80%) is an AI HPC integrator. SIMO (+189% YTD) pivoted from mobile storage controllers to enterprise AI SSD controllers. EARNINGS CATALYSTS (near-term triggers): - MXL: +85% single day April 24 — optical/AI revenue +136% YoY, raised guidance - SIMO: +massive April 29 — EPS $1.58 vs $1.30, enterprise AI boot drives +200% QoQ - AXTI: April 30 — InP backlog $100M+, margin expansion, Q2 guidance beat vs loss expected - AEHR: $41M record order April 16 from hyperscale AI customer for silicon photonics burn-in - AAOI: $324M+ backlog including $200M+ single 1.6T order from hyperscaler All are supply-chain reads on the same hyperscaler AI capex cycle.

InP (Indium Phosphide) is a compound semiconductor made from indium and phosphorus. Unlike silicon, InP has a direct bandgap, meaning it efficiently emits and modulates light at the wavelengths used in fiber optic communication (1310nm and 1550nm). This makes InP the irreplaceable material for: - High-speed optical transceivers (400G, 800G, 1.6T) - Coherent optical chips (used in long-haul and data center interconnects) - Silicon photonics laser sources (external light sources for on-chip photonics) - Co-packaged optics (CPO) laser arrays WHY SUDDENLY CRITICAL FOR AI: As GPU clusters scale to 100,000+ cards, copper interconnects hit a power and bandwidth wall. Every AI server must connect via optical transceivers. A single hyperscaler AI cluster needs hundreds of thousands of transceivers. Each transceiver needs InP lasers. Demand has exploded faster than InP wafer capacity can scale. KEY COMPANIES: - AXTI (AXT Inc): One of the only large-scale InP wafer manufacturers globally. Beijing Tongmei subsidiary. Backlog >$100M, raising $632M to expand capacity. - SIVEF (Sivers Semiconductors): Swedish company making InP laser arrays for CPO and silicon photonics. Partnership with O-Net/Enablence for CPO external light sources. - Compound semiconductor foundries: IQE (UK), WIN Semiconductors (Taiwan) also relevant. GEOPOLITICAL NOTE: Indium is partially sourced from China (byproduct of zinc smelting). InP wafer manufacturing is concentrated in a few companies globally. Supply tightness + AI demand surge = major pricing power for AXTI and similar.

AEHR Test Systems makes burn-in and reliability test equipment — specifically the FOX-XP platform, which runs chips at elevated temperature and voltage stress for hours/days before deployment to catch early-life failures (infant mortality). This is standard practice for high-reliability applications. WHY AI OPTICAL MAKES AEHR CRITICAL: 1. Silicon photonics chips (the optical engines inside CPO and advanced transceivers) are compound semiconductor devices. Unlike standard CMOS, they cannot be fixed in the field. A failed optical chip in a hyperscaler AI cluster causes rack downtime. 2. Hyperscalers require 100% burn-in testing of every silicon photonics chip before deployment — non-negotiable for uptime SLAs. 3. As 800G/1.6T transceiver volumes explode (AAOI targeting 500K units/month by end-2026), every unit needs AEHR-style burn-in testing. 4. AEHR also recently won custom AI ASIC burn-in orders — hyperscalers are now burn-in testing their custom AI chips (TPUs, Trainium, etc.) at wafer level. 2026 CATALYSTS: - New silicon photonics customer win (March 31): +23% single day - $41M record order from hyperscale AI customer (April 16): largest in company history - H2 FY2026 bookings >$92M; backlog $50.9M record - Returning to profitability in Q4 ANALOGY: AEHR is to silicon photonics what KLA is to advanced logic — the unavoidable quality control step at scale.

LPKF is a German precision laser equipment company (founded 1976, Frankfurt: LPK, OTC: LPKFF). Their relevant technology for 2026 is LIDE — Laser-Induced Deep Etching. WHAT LIDE DOES: Uses ultrafast lasers to modify glass, then wet etching to create extremely precise micro-holes (vias) in glass sheets. This is the critical enabling step for glass core substrates — the next-generation semiconductor packaging platform that Intel, TSMC, Samsung Electro-Mechanics, and others are developing as a replacement for organic (resin) substrates. WHY GLASS SUBSTRATES MATTER FOR AI CHIPS: - Organic substrates (FR4/ABF) have thermal expansion mismatch with silicon — limits how many chiplets can be tiled - Glass has near-zero thermal expansion mismatch — allows much larger, more complex packages - Glass enables finer pitch interconnects — more signals per mm² - Critical for AI accelerator packaging where GPU die + HBM + optical engines must all be co-packaged - Intel calls it "Glass Core Technology"; TSMC is developing glass-based CoWoS variants LPKF MOAT: They and one smaller German competitor are the only companies in the world with a proven, production-ready LIDE process. When glass substrate volume production ramps (~2027-2029), LPKF becomes a near-monopoly capital equipment supplier. WHY THE STOCK RALLIED 300%: Entirely forward-looking. The AI infrastructure capex narrative pulled the timeline forward in investors minds. LPKF is pre-revenue on glass substrates — current revenue is €105-120M guidance from legacy PCB laser tools. The glass substrate story is a 2027-2029 revenue event being priced in now. CONNECTION: Glass substrates are the next generation of what TSMC CoWoS does today. Both enable chiplet + HBM co-packaging. Glass enables the transition beyond current CoWoS limits.

Stage 1 — Raw Materials: Quartz sand → ultra-pure polysilicon (11N purity) → single crystal silicon ingot (Czochralski process) → sliced 300mm wafers. Key suppliers: Wacker Chemie (Germany), Hemlock (US) for polysilicon; Shin-Etsu and SUMCO (Japan) dominate 300mm wafers. Stage 2 — Chip Design (EDA): Synopsys (SNPS) and Cadence (CDNS) are the two dominant EDA tool providers. Without EDA software, you cannot design any chip below 28nm. ARM Holdings provides CPU instruction set architecture; Nvidia designs its own GPU architecture (CUDA). Stage 3 — Photomasks: Circuit patterns etched onto glass stencils. Hoya and AGC (Japan) make EUV mask blanks. Carl Zeiss (Germany) makes EUV pellicles. KLA (KLAC) inspects masks. Stage 4 — Lithography (most critical): ASML (Netherlands) has monopoly on EUV (13.5nm wavelength, ~$380M/machine). EUV enables 7nm and below efficiently. DUV (193nm) from ASML/Nikon/Canon handles 28nm+, and 7nm with expensive multi-patterning. Stage 5 — Deposition + Etch (hundreds of steps): Applied Materials (AMAT) — CVD, ALD, PVD, CMP. Lam Research (LRCX) — plasma etch, ALD. Tokyo Electron (TEL) — etch, CVD, track. Stage 6 — Inspection at every critical step: KLA Corp (KLAC) — wafer defect inspection, overlay metrology, process control. Without KLA, yield collapses. Stage 7 — Specialty Materials: Photoresists (JSR, Shin-Etsu, TOK — all Japan). Specialty gases (Air Products, Linde, Air Liquide). CMP slurries (Entegris/ENTG, Fujimi). Stage 8 — Wafer Fab: TSMC 4N process for Nvidia GPU die. TSMC is sole provider of leading-edge logic for Nvidia, Apple, AMD, Qualcomm. Stage 9 — Advanced Packaging (CoWoS): TSMC packages the GPU die + HBM stacks on a silicon interposer using CoWoS (Chip on Wafer on Substrate). This is unique to TSMC. SK Hynix provides HBM3E memory stacks. Stage 10 — Test: Teradyne (TER) for logic test; Advantest (Japan) for memory/HBM test. For an Nvidia B200: Two GPU dies (TSMC 4NP) + HBM3E (SK Hynix) + CoWoS packaging (TSMC) + NVLink-C2C die-to-die interconnect.

China has leverage in raw materials, not in advanced manufacturing tools or design. GALLIUM (China ~80% of global supply): Used in GaN semiconductors, RF chips, LEDs, power devices. China imposed export controls August 2023. No major alternative supply exists short-term. Companies most exposed: RF chip makers, power device companies. GERMANIUM (China ~60%): Fiber optic cables, infrared optics, some semiconductor substrates. Export controls August 2023. TUNGSTEN (China ~80%): Sputtering targets used in physical vapor deposition (chip metallization). Latent leverage — not yet weaponized. ANTIMONY (China ~50%): Flame retardants, some compound semiconductors. Export controls August 2024. RARE EARTH ELEMENTS (China ~85% of processing): Magnets, phosphors, lasers. Critical for motors, speakers, EV batteries. China mines ~60% and processes ~85% globally. Less direct chip impact but critical for the broader electronics ecosystem. FLUORSPAR (China ~60%): Source material for hydrofluoric acid (HF) used extensively in chip etching. Less attention but real exposure. POLYSILICON (GCL Poly is world-largest): Primarily solar grade; electronics-grade still dominated by Wacker/Hemlock/Tokuyama. Less of a current leverage point. MATURE NODE CAPACITY: China is building enormous 28nm fabs (SMIC, Nexchip, Huali). By 2026-27 they will flood the market with cheap mature-node chips for automotive, IoT, industrial. This threatens Western foundries at mature nodes (GlobalFoundries, UMC) but not at advanced nodes. CONVENTIONAL PACKAGING: JCET and Tongfu are world-scale OSAT providers. China has real strength here for conventional (non-advanced) packaging. BOTTOM LINE: China's leverage is in the ground (minerals), not in the fab. Western strategy is to diversify materials sourcing (MP Materials, Energy Fuels) while maintaining tool + foundry dominance.

THE SUPREME CHOKEPOINTS (China completely blocked): 1. ASML (Netherlands, ASML) — EUV lithography. Only company on earth making EUV machines. China blocked since 2019. Advanced DUV (NXT:2000i+) also restricted since Jan 2024. Without EUV, China cannot efficiently make chips below 7nm. SMEE (China's domestic attempt) is at ~90nm; 28nm is a distant goal. 2. Synopsys (SNPS) + Cadence (CDNS) — EDA tools. Restricted from selling advanced EDA to Chinese chip designers. Without updated EDA, Chinese companies cannot design leading-edge chips. Their HiSilicon/Huawei designs are frozen on older tool versions. 3. TSMC (TSM) — advanced foundry. Stopped taking orders for advanced nodes from Chinese customers. SMIC cannot replace TSMC's sub-7nm capability. 4. SK Hynix / Micron (MU) — HBM memory. China has zero HBM capability (CXMT cannot make it). Huawei Ascend 910B uses LPDDR5 instead of HBM — severe bandwidth bottleneck for AI training. 5. Applied Materials (AMAT) + Lam Research (LRCX) + KLA (KLAC) — equipment. Restricted from selling advanced tools to China's cutting-edge fabs. Also restricted from SERVICING existing tools in China's advanced fabs — critical because these machines require constant calibration. 6. Japan aligned (Tokyo Electron TEL, JSR, Shin-Etsu, photoresist makers) — export controls on EUV photoresists, advanced equipment, specialty chemicals. HOW CHINA IS RESPONDING: - SMEE: Building domestic lithography (~90nm now, targeting 28nm). Faces fundamental physics + supply chain constraints on the laser source, optics (needs Zeiss-quality mirrors), and controls. - NAURA + AMEC: Domestic etch and CVD equipment. Genuine progress at mature nodes (28nm+). - SMIC 7nm via DUV multi-patterning: Achieved for Huawei Kirin 9000S (Mate 60 Pro, 2023). Technically impressive but low yield and expensive. Cannot scale below 5nm. - YMTC: NAND flash 232-layer. Actually competitive with Samsung/Micron at mature NAND. Not relevant for AI (which needs HBM, not NAND). - CXMT: DRAM at ~19nm vs Samsung/Hynix at 12nm. Significant gap. - Huawei Ascend 910B: Domestic AI chip, claims ~80% H100 training performance (disputed). Real weakness is no HBM — interconnect bandwidth is the wall. - RISC-V: Dozens of Chinese companies building RISC-V CPUs to escape ARM/x86 licensing. - Big Fund III (2024): ~$47B government investment fund for domestic semiconductor industry. - Hoarding: China stockpiled DUV tools, advanced memory, and Nvidia GPUs before each export control tightening. - Routing: Buying chips through Malaysia, Singapore, Middle East intermediaries (US cracking down on this). VERDICT: China is making real progress at 28nm+ mature nodes and in NAND flash. At advanced nodes (<7nm), HBM, and advanced packaging, the gap is widening not narrowing because the West keeps restricting more tools and China's domestic alternatives are 7-10 years behind.

HBM is the key memory technology that makes AI GPUs fast enough to be useful for training large models. WHY HBM EXISTS: A GPU's CUDA cores can process data faster than conventional DRAM (DDR5) can feed them. Standard DRAM is connected via a narrow bus. HBM solves this by stacking multiple DRAM dies vertically (using Through-Silicon Vias / TSVs) and placing them on the same silicon interposer as the GPU die via TSMC's CoWoS packaging. The "bus" becomes thousands of parallel connections just millimeters wide. SPECS COMPARISON: - DDR5: ~100 GB/s bandwidth - LPDDR5 (Huawei Ascend uses this): ~200 GB/s - HBM3E (H200): 5.4 TB/s — 27x more bandwidth than DDR5 For LLM training, the model weights must be constantly moved in and out of memory. Bandwidth = training speed. HBM is not optional for competitive AI training performance. SUPPLY CHAIN: SK Hynix (Korea) is the dominant HBM3E supplier and Nvidia's primary source. Samsung is qualifying HBM3E late. Micron (MU) is the US supplier — critical for national security diversification. TSMC does the CoWoS packaging that integrates HBM + GPU die. HBM4 (coming 2025-2026): SK Hynix and Samsung competing. Higher bandwidth, lower power. TSMC will do packaging. CHINA: CXMT (ChangXin Memory) makes DRAM at 19nm node. No TSV capability, no HBM. This is a complete wall for China's AI chip ambitions. Even if SMIC could make a competitive GPU die, there is no Chinese HBM to pair with it. The Ascend 910B's real-world AI training performance is severely limited by this.

Traditional AI cluster networking uses pluggable transceivers (QSFP-DD, OSFP) on the switch faceplate. At scale — 100,000+ GPU clusters — the electrical trace from ASIC to faceplate consumes 15–20W per port and creates a power/bandwidth wall you cannot scale past. CPO moves the optical engine directly onto the switch ASIC package, shrinking that electrical trace from ~30cm to ~3mm. Result: 30–50% power reduction and 4x+ bandwidth density improvement, enabling 800G and 1.6T per port economically.

Switch ASICs (the hub): Marvell (MRVL) with Teralynx 10 is the most advanced CPO roadmap in merchant silicon; Broadcom (AVGO) competes with Tomahawk 5. Optical engines: Coherent (COHR) is the leading transceiver maker (800G ZR, 1.6T), vertically integrated after acquiring Finisar and II-VI. Laser sources: Lumentum (LITE) supplies pump lasers for CPO optical engines. Advanced packaging equipment: Applied Materials (AMAT) for glass substrates, Lam Research (LRCX) for ALD/etch, KLA (KLAC) for inspection. Contract manufacturing: Fabrinet (FN) assembles transceivers at volume. Adjacent: Credo Technology (CRDO) for active electrical cables within rack.

Meta is piloting CPO switches internally, targeting 2025–26 AI cluster deployment. Microsoft is committed — OpenAI cluster specs include CPO with Marvell Teralynx design wins. Google is in deep co-design with Marvell on Teralynx CPO for TPU pod networking. Amazon (AWS) is still evaluating, watching CPO for Graviton cluster expansion alongside their own Trainium silicon. The market inflection is 2025–2027 as hyperscaler qualification cycles complete and volume ramps begin.

LightCounting (2024 estimates): CPO addressable market ~$3B by 2027, growing to $10B+ by 2030. The traditional pluggable transceiver market is ~$15B today and is being partially displaced, but CPO is also additive — AI clusters are net-new bandwidth demand, not a direct 1:1 substitution. The equipment supply chain (AMAT, LRCX, KLAC) benefits from CPO increasing packaging complexity, which drives tool intensity per wafer.